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1  Ultimate Audio Playback / Phasure NOS1 DAC / Re: Power Supply Noise measurement on: May 16, 2014, 10:40:41 am
Hi Peter,

No need to worry about dBV, you've given the important bit of missing info, 2.25V = 0dBFS was all I really needed to convert the above numbers to absolute voltages. I was more interested in what happens to red plot when signal plays, wouldn't expect white to change. Was trying to compare this with the measurements earlier this year that you showed in the NOS1-USB thread.

Chris
2  Ultimate Audio Playback / Phasure NOS1 DAC / Re: Power Supply Noise measurement on: May 16, 2014, 03:12:54 am
Peter,

What is your FS set to in these measurements? (might be more meaningful for comparisons in say dBV)

What happens to the noise floor when you put a test tone say 1kHz through rather than silence?


Cheers,
Chris
3  Ultimate Audio Playback / Phasure NOS1 DAC / Re: Jitter on: May 12, 2014, 02:09:25 am
Hi Peter,

I am Chris/hochopeper from SNA, Anthony mentioned this post to me and I enjoyed reading, thank you for sharing details of your experiment. I first read this post in detail while watching the Catalunya F1 GP so I may have missed some of the details in your post so I'll give it a read (and possibly a 3rd read for good measure) before I respond in detail.

One thing that I thought while reading was: Have you been able to take a freq domain measurement of the DAC output for any of these scenarios? If yes, did it simply show nothing of interest?


Not only that but there are several parts of this that I am going to have to re-read to fully comprehend but I believe you just showed a mechanism by which a solid state device is susceptible to vibration.  Again wow!

Hi Anthony,

There has been some discussion in low noise regulator design datasheets that I've read that piezoelectric effect of some capacitor types can impact noise performance in a circuit. These capacitors are the same ones that are absolutely vital in their performance for the clock to perform well. I've read papers/discussion where different decoupling designs give dramatic improvements to clocks as well as jitter on the output of CPLD/FPGA processors.


Regards,
Chris
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